Testability-driven High-level Synthesis

This paper describes a new approach to integrate testability consideration into high-level synthesis. The approach is based on an iterative technique for high-level synthesis which utilizes a sequence of design-improvement transformations to generate a register-transfer level design from a VHDL behavioral specification. A testability analysis algorithm is used to analyze the intermediate results of the transformation process. Based on the analysis results, appropriate testability-improvement techniques are selected and applied to the most test-resistant parts of the design. Three main techniques are used for testability improvement: controllability/observability-balance allocation, partial scan, and condition scan. Since the application of testability-improvement transformations is carried out together with operation scheduling, data path allocation, and control allocation, the testability factor is taken into account in the global optimization process and more testable designs are generated.